module CPUv2(
	input    [0:0]  clk,
	input	 [0:0]  rst,

	// output   [31:0] o_id_pc,
	// output   [31:0] o_id_inst,
	// output   [31:0] o_ex_Addr,
	// output   [31:0] o_mem_Addr,
	// output   [31:0] o_wb_Addr,
	// output   [7:0]  o_ex_CtrlCode,
	// output   [7:0]  o_mem_Code,
	// output   [7:0]  o_wb_Code,
	// output   [31:0] o_ex_RFRead0,
	// output   [31:0] o_ex_RFRead1,
	// output   [31:0] o_wb_OData,
	// output   [31:0] o_wb_RFWAddr,
	// output   [31:0] o_mem_ALURes,
	// output   [31:0] o_ex_JumpAddr,
	// output   [31:0] o_ex_BranchAddr,
	output   [31:0] wb_Pin
);

wire [31:0] if_pc;
wire [31:0] id_pc;
wire [31:0] id_inst;

wire [31:0] wb_Wdata;
wire [31:0] wb_Waddr;
wire        wb_Wsinal;

wire [31:0] ex_JumpAddr;
wire [31:0] ex_BranchAddr;
wire [7:0]  ex_AluCode;
wire [31:0] ex_RFRead0;
wire [31:0] ex_RFRead1;
wire [7:0]  ex_CtrlCode;
wire [31:0] ex_RFWAddr;
wire [31:0] ex_Addr;
wire [31:0] ex_WrData;

wire [31:0] mem_JumpAddr;
wire [31:0] mem_Addr;
wire [7:0]  mem_Code;
wire [31:0] mem_ALURes;
wire [31:0] mem_WrData;
wire [31:0] mem_RFWAddr;

wire [31:0] wb_Addr;
wire [7:0]  wb_Code;
wire [31:0] wb_OData;
wire [31:0] wb_RFWAddr;

wire [7:0]  Code;
wire [31:0] RFWAddr;

// assign o_id_pc = id_pc;
// assign o_id_inst = id_inst;
// assign o_ex_Addr = ex_Addr;
// assign o_mem_Addr = mem_Addr;
// assign o_wb_Addr = wb_Addr;
// assign o_ex_CtrlCode = ex_CtrlCode;
// assign o_mem_Code = mem_Code;
// assign o_wb_Code = wb_Code;
// assign o_ex_RFRead0 = ex_RFRead0;
// assign o_ex_RFRead1 = ex_RFRead1;
// assign o_wb_OData = wb_OData;
// assign o_wb_RFWAddr = wb_RFWAddr;
// assign o_mem_ALURes = mem_ALURes;
// assign o_ex_JumpAddr = ex_JumpAddr;
// assign o_ex_BranchAddr = ex_BranchAddr;

if_id inst_if_id (
	.clk(clk),
	.rst(rst),
	.if_pc(if_pc),
	.id_pc(id_pc),
	.id_inst(id_inst)
);

id_ex inst_id_ex (
	.clk           (clk),
	.rst           (rst),
	.id_pc         (id_pc),
	.id_inst       (id_inst),
	.wb_wdata      (wb_Wdata),
	.wb_waddr      (wb_Waddr),
	.wb_wsinal     (wb_Wsinal),

	.ex_JumpAddr   (ex_JumpAddr),
	.ex_BranchAddr (ex_BranchAddr),
	.ex_AluCode    (ex_AluCode),
	.ex_RFRead0    (ex_RFRead0),
	.ex_RFRead1    (ex_RFRead1),
	.ex_CtrlCode   (ex_CtrlCode),
	.ex_RFWAddr    (ex_RFWAddr),
	.ex_Addr       (ex_Addr),
	.ex_WrData	   (ex_WrData)
);

ex inst_ex (
	.clk           (clk),
	.rst           (rst),
	.ex_JumpAddr   (ex_JumpAddr),
	.ex_BranchAddr (ex_BranchAddr),
	.ex_Addr       (ex_Addr),
	.ex_Code       (ex_CtrlCode),
	.ex_RFRead1    (ex_RFRead0),
	.ex_RFRead2    (ex_RFRead1),
	.ex_WrData     (ex_WrData),
	.ex_CtrlCode   (ex_AluCode),
	.ex_RFWAddr    (ex_RFWAddr),

	.mem_JumpAddr  (mem_JumpAddr),
	.mem_Addr      (mem_Addr),
	.mem_Code      (mem_Code),
	.mem_ALURes    (mem_ALURes),
	.mem_WrData    (mem_WrData),
	.mem_RFWAddr   (mem_RFWAddr)
);

mem inst_mem (
	.clk          (clk),
	.rst          (rst),
	.mem_JumpAddr (mem_JumpAddr),
	.mem_Addr     (mem_Addr),
	.mem_Code     (mem_Code),
	.mem_ALURes   (mem_ALURes),
	.mem_WrData   (mem_WrData),
	.mem_RFWAddr  (mem_RFWAddr),
	.wb_Addr      (wb_Addr), 
	.wb_Code      (wb_Code),
	.wb_OData     (wb_OData),
	.wb_RFWAddr   (wb_RFWAddr),
	.wb_Pin       (wb_Pin)
);

wb inst_wb (
	.clk        (clk),
	.rst        (rst),
	.wb_Addr    (wb_Addr),
	.wb_Code    (wb_Code),
	.wb_OData   (wb_OData),
	.wb_RFWAddr (wb_RFWAddr),
	.Addr       (if_pc),
	.Code       (Code),
	.OData      (wb_Wdata),
	.RFWAddr    (RFWAddr)
);


assign wb_Waddr = RFWAddr;
// assign wb_Wdata = RFWAddr;
assign wb_Wsinal = Code[0];
endmodule
